Ferroelectric random access memory

ABSTRACT

A ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of word lines extending in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an M×N array while being connected to associated ones of the lines. The unit cells are grouped into a plurality of unit cell groups. A dummy cell group comprises a plurality of dummy cells that are connected to an associated one of the bit lines of an optional position on the associated bit line. A first switching transistor group comprises a plurality of switching transistors that serve to switch a connection among associated ones of the unit cells on one of the bit lines corresponding to an associated one of the dummy cells in response to a control signal externally applied thereto, and a second switching transistor group comprises a plurality of switching transistors that serve to erase data stored in an associated one of the dummy cells in response to a control signal externally applied thereto. Respective capacitors of the dummy cells are made of a dielectric film having no spontaneous polarization characteristic.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the priority of Korean patent application SerialNo. 99-42045 filed on Sep. 30, 1999.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a ferroelectric memory device, and moreparticularly to a ferroelectric random access memory device fabricatedusing a ferroelectric material having a perovskite structure to obtainan enhanced reliability when data is read out.

2. Description of the Related Art

As well known, semiconductor memory devices are classified into volatilememory devices and non-volatile memory devices in accordance withwhether or not information is lost when power is off. A dynamic randomaccess memory (DRAM), which is a volatile memory, is configured to keepinformation only in a power-on state even though it has a high operatingspeed. Such a DRAM also has a drawback in that the consumption of poweris excessive because refreshing of data should be carried out atintervals of a certain time in order to prevent data from being lost dueto leakage current from a charge transfer transistor coupled to acapacitor. Meanwhile, EEPROMs and flash memories, which are non-volatilememories, have drawbacks of a low operating speed and an excessive powerconsumption even though data can kept in a power-off state.

On the other hand, a ferroelectric random access memory (FeRAM) hasadvantages in that they have an operating speed similar to that of DRAMswhile exhibiting a reduced power consumption. Such an FeRAM is anon-volatile memory capable of keeping data even in a power-off state,like EEPROMs and flash memories. By virtue of these advantages, such anFeRAM has recently been recognized as a substitutive memory for DRAMs,EEPROMs, flash memories, and other semiconductor memories. In accordancewith such a recognition, active research and development have been madefor FeRAMs in many companies and research institutes in the world.

Such an FeRAM uses a capacitor made of a ferroelectric film, such asPZT(Pb(Zr, Ti)O₃ or SBT(SrBi₂Ta₂O₉), having spontaneous polarizationcharacteristics capable of maintaining a polarization generated inaccordance with an application of a certain voltage, even after power isoff. Such an FeRAM utilizes the hysteretic characteristics of aferroelectric depicted in FIG. 1.

Referring to FIG. 1, the ferroelectric is polarized when a voltage Vapplied to the ferroelectric is increased in a plus (+) direction, sothat it exhibits a maximum polarized value Qmax at a maximum voltage.When the applied voltage is cut off, the residual polarization of theferroelectric corresponds to “Qr”. This residual polarization value Qrcorresponds to data “1”. When the voltage V is decreased in a minus (−)direction, the ferroelectric is polarized in an opposite direction, sothat it exhibits a minimum polarized value Qmin at a minimum voltage.When the applied voltage is cut off in this state, the residualpolarization of the ferroelectric corresponds to “−Qr”. This residualpolarization value −Qr corresponds to data “0”.

Here, the “+” and “−” directions of the voltage V are indicative ofdifferent relative potential relations between the upper and lowerelectrodes of the capacitor, respectively. The “+” direction means thatthe upper electrode has a potential relatively higher than that of thelower electrode. The “−” direction means that the upper electrode has apotential relatively lower than that of the lower electrode.

This will be described in more detail, in conjunction with FIG. 6 whichis a circuit diagram illustrating the equivalent circuit of aconventional FeRAM. In order to store data “1” in a capacitor of a unitcell UC in the circuit of FIG. 5, a potential, which is higher than thatapplied to a plate electrode, is applied to a bit line in an ON state ofa charge transfer transistor, thereby causing a ferroelectric to bespontaneously polarized. After the spontaneous polarization of theferroelectric, the charge transfer transistor is turned off, so thatdata “1” is stored. On the other hand, data “0” is stored by applying,to the bit line, a potential lower than the potential applied to theplate electrode in the ON state of the charge transfer transistor,thereby spontaneously polarizing the ferroelectric, and then turning offthe charge transfer transistor.

When data stored in the capacitor is to be read out from the memory, thecharge transfer transistor is turned off in a state in which a potentialhigher than that applied to the plate electrode is applied to the bitline. As a result, a charge dQ1 is discharged into the bit line when thedata stored in the capacitor is “1”. When the data stored in thecapacitor is “0”, a charge dQ0 is discharged into the bit line. That is,the potential of the bit line varies in accordance with the value of thedata stored in the capacitor because the charge discharged into the bitline varies in accordance with the value of the stored data.

When the data stored in the capacitor is “1”, the potential variation V1on the bit line corresponds to “dQ1/ (Cb +Cs)” (V1=dQ1/(Cb+Cs)). On theother hand, the data stored in the capacitor is “0”, the potentialvariation V0 on the bit line corresponds to “dQ0/(Cb+Ca)”(V0=dQ0/(Cb+Cs)). Therefore, it is possible to determine the data (“1”or “0”) by comparing the potential on the bit line, outputted at anoutput terminal (not shown) of the memory, with a reference potential.

The conventional FeRAM shown in FIG. 6 consists of unit cells UC eachhaving a 1T/1C structure including one transistor and one capacitor.

Referring to FIG. 6, the FeRAM includes M+N unit cells. Each unit cellUC consists of one transistor (a charge transfer transistor), and onecapacitor. The transistor of each unit cell UC is coupled at a gatethereof to an associated one of word lines WL0, WL1, and WL2, at a drain(or a source) thereof to an associated one of bit lines BL0 and BL1, andat a source (a drain) thereof to one end of the capacitor included inthe unit cell UC. The other end of the capacitor is connected to anassociated one of plate electrode lines PL0, PL1 and PL2. Each bit lineBL0 or BL1 is coupled at one end thereof to an associated one ofcomparators C0 and C1.

The above mentioned convention FeRAM also includes a reference voltagegenerating circuit. This reference voltage generating circuit includestwo switching transistors ST0 and ST1, and two dummy cells DC0 and DC1.Each of the dummy cells DC0 and DC1 consists of one transistor (a chargetransfer transistor), and one capacitor. Respective transistors of thedummy cells DC0 and DC1 are coupled at their drains (or sources) todummy bit lines DBL and /DBL, and coupled to each other via switchingtransistors ST0 and ST1 respectively connected to the dummy bit linesDBL and /DBL, thereby forming a common output. The common output fromthe switching transistors ST0 and ST1 is coupled to the other input ofeach of the comparators C0 and C1.

That is, each of the comparators C0 and C1 is coupled at one inputthereof to an associated one of the bit lines BL0 and BL1, and at theother input thereof to the common output of the dummy bit lines DBL and/DBL. Accordingly, each comparator C0 or C1 determines data (“0” or “1”)outputted from an optional unit cell UC by comparing the voltage of theunit cell UC, applied thereto via the associated bit line, with areference voltage applied thereto from the common output of theswitching transistors ST0 and ST1.

Meanwhile, a ferroelectric film, which is used for an FeRAM having theabove mentioned configuration, exhibits an inferior resistance to afatigue degradation over a typical capacitor. For this reason, thenumber of repeated write times of such a ferroelectric film is typically10¹² less than that of typical capacitors, that is, 10¹⁵.

In the above mentioned convention FeRAM, the dummy cells DC0 and DC1 areused every time data is stored in or read out from associated unitcells, respectively. For this reason, these dummy cells are used for thenumber of times considerably more than that of each unit cell in whichdata is actually stored. As a result, the dummy cells may be degradedearlier than the unit cells.

For example, in the case of an FeRAM including 256 K unit cells, thatis, an FeRAM having a unit memory block arrangement in which 256 unitcells are arranged on one bit line, and 1,024 unit cells are arranged onone word line, each dummy cell conducts a read or write procedure for256 K times when one unit cell conducts a read or write procedure once.

The number of repeated using times actually allowed in a semiconductormemory is determined, not based on the unit cell, but based on the dummycell. For this reason, the number of repeated using times actuallyallowed in an FeRAM is determined, not to be 10¹², which is antheoretical value, but to be 10⁷. In other words, the conventional FeRAMhaving a 1T/1C structure has a problem in that the actual number ofrepeated using times is considerably less than the theoretical number ofrepeated using times.

FIG. 7 is an equivalent circuit diagram illustrating a part of aconventional FeRAM having a 2T/2C structure consisting of twotransistors and two capacitors.

The FeRAM shown in FIG. 7 configures each unit cell UC by twotransistors (charge transfer transistors) and two capacitors in such afashion that a reference voltage to be compared with the potential of abit line adjacent to the unit cell UC is generated from the unit cellUC, as compared to the FeRAM of FIG. 6 including a separate referencevoltage generating circuit.

Since each unit cell UC generates a reference voltage to be comparedwith the potential of a bit line adjacent thereto, the FeRAM having the2T/2C structure can eliminate the problems involved in the FeRAM havingthe 1T/1C structure, that is, an RC delayer and a drop of the referencevoltage.

However, the FeRAM having the 2T/2C structure has an increased unit cellsize because two charge transfer transistors are formed for each unitcell. As a result, this FeRAM has a fatal problem in that it isimpossible to achieve a high integration.

SUMMARY OF THE INVENTION

A first object of the invention is to provide an FeRAM capable ofallowing the number of times using a dummy cell to correspond to thenumber of times using a unit cell, thereby preventing the number oftimes repeatedly using the memory to be reduced.

A second object of the invention is to provide an FeRAM capable ofpreventing the number of times repeatedly using the memory to bereduced, while easily achieving a high integration.

A third object of the invention is to provide an FeRAM capable ofachieving a high integration and an increase in capacitance.

In accordance with one aspect, the present invention provides aferroelectric random access memory comprising a plurality of bit linesextending in one direction, a plurality of word lines extending inanother direction perpendicular to the one direction, and a plurality ofunit cells arranged in an M+N array while being connected to associatedones of the lines, each of the unit cells consisting of one transistorand one capacitor, wherein the unit cells are grouped into a pluralityof unit cell groups, each of the unit cell groups consisting of aplurality of unit cells connected to associated ones of the bit lines,respectively, in such a fashion that they are arranged in an interlacedfashion in a row direction or in a column direction, those of the bitlines connected to each of the bit lines being connected together inseries; further comprising: a dummy cell group consisting of a pluralityof dummy cells each connected to an associated one of the bit lines atan optional position on the associated bit line, each of the dummy cellsconsisting of one transistor and one capacitor; a first switchingtransistor group consisting of a plurality of switching transistors eachserving to switch a connection among associated ones of the unit cellson one of the bit lines corresponding to an associated one of the dummycells in response to a control signal externally applied thereto; and asecond switching transistor group consisting of a plurality of switchingtransistors each serving to erase data stored in an associated one ofthe dummy cells in response to a control signal externally appliedthereto; wherein respective capacitors of the dummy cells are made of adielectric film having no spontaneous polarization characteristic;whereby when data is read out from an optional one of the unit cells ona selected one of the bit lines, a predetermined voltage outputted fromthat of dummy cells connected to an inverted bit line neighboring to theselected bit line is provided as a reference voltage required for acomparison with a voltage corresponding to the read-out data.

In accordance with another aspect, the present invention provides aferroelectric random access memory comprising a plurality of bit linesextending in one direction, a plurality of word lines extending inanother direction perpendicular to the one direction, and a plurality ofunit cells arranged in an M×N array while being connected to associatedones of the lines, each of the unit cells consisting of one transistorand one capacitor, wherein the unit cells are grouped into a pluralityof unit cell groups, each of the unit cell groups consisting of aplurality of unit cells connected to associated ones of the bit lines,respectively, in such a fashion that they are arranged in an interlacedfashion in a row direction or in a column direction, those of the bitlines connected to each of the bit lines being connected together inseries; wherein the bit lines are arranged in pair, each of the bit linepairs consisting of two bit lines; further comprising: a dummy cellgroup consisting of a plurality of dummy cells each connected to one ofbit lines included in an associated one of the bit line pairs at anoptional position on the bit line, each of the dummy cells consisting ofone transistor and one capacitor; a first switching transistor groupconsisting of a plurality of switching transistors each serving toswitch a connection among the unit cells on one bit line included in anassociated one of the bit line pairs respectively corresponding to thedummy cells in response to a control signal externally applied thereto;a second switching transistor group consisting of a plurality ofswitching transistors each serving to switch a connection between thebit lines included in an associated one of the bit line pairsrespectively corresponding to the dummy cells in response to a controlsignal externally applied thereto, the switching transistors of thesecond switching transistor group corresponding in number to the dummycells; and a third switching transistor group consisting of a pluralityof switching transistors each serving to erase data stored in anassociated one of the dummy cells in response to a control signalexternally applied thereto; wherein respective capacitors of the dummycells are made of a dielectric film having no spontaneous polarizationcharacteristic; whereby when data is read out from an optional one ofthe unit cells on a selected one of the bit lines, a predeterminedvoltage outputted from that of dummy cells connected to the bit linepair including the selected bit line is provided pair as a referencevoltage required for a comparison with a voltage corresponding to theread-out data.

In accordance with another aspect, the present invention provides aferroelectric random access memory comprising a plurality of bit linesextending in one direction, a plurality of word lines extending inanother direction perpendicular to the one direction, and a plurality ofunit cells arranged in an M×N array while being connected to associatedone of the lines, each of the unit cells consisting of one transistorand one capacitor, wherein the unit cells are grouped into a pluralityof unit cell groups, each of the unit cell groups consisting of aplurality of unit cells connected to associated ones of the bit lines,respectively, in such a fashion that they are arranged in an interlacedfashion in a row direction or in a column direction, those of the bitlines connected to each of the bit lines being connected together inseries; wherein the bit lines are grouped into bit line groups eachconsisting of N bit lines; further comprising: a dummy cell groupconsisting of a plurality of dummy cells each connected to one of bitlines included in an associated one of the bit line pairs at an optionalposition on the bit line, each of the dummy cells consisting of onetransistor and one capacitor; a first switching transistor groupconsisting of a plurality of switching transistors each serving toswitch a connection among the unit cells on one bit line included in anassociated one of the bit line groups respectively corresponding to thedummy cells in response to a control signal externally applied thereto;a second switching transistor group consisting of a plurality ofswitching transistors each serving to switch a connection between thebit lines included in an associated one of the bit line groupsrespectively corresponding to the dummy cells in response to a controlsignal externally applied thereto; and a third switching transistorgroup consisting of a plurality of switching transistors each serving toerase data stored in an associated one of the dummy cells in response toa control signal externally applied thereto; wherein respectivecapacitors of the dummy cells are made of a dielectric film having nospontaneous polarization characteristic; whereby when data is read outfrom an optional one of the unit cells on a selected one of the bitlines, a predetermined voltage outputted from an inverted bit lineneighboring to the bit line group including the selected bit line isprovided as a reference voltage required for a comparison with a voltagecorresponding to the read-out data.

In accordance with another aspect, the present invention provides aferroelectric random access memory comprising a plurality of bit linesextending in one direction, a plurality of word lines extending inanother direction perpendicular to the one direction, and a plurality ofunit cells arranged in an M×N array while being connected to associatedones of the lines, each of the unit cells consisting of one transistorand one capacitor, wherein the unit cells are grouped into a pluralityof unit cell groups, each of the unit cell groups consisting of aplurality of unit cells connected to associated ones of the bit lines,respectively, in such a fashion that they are arranged in an interlacedfashion in a row direction or in a column direction, those of the bitlines connected to each of the bit lines being connected together inseries; further comprising: a dummy cell group divided into a firstdummy cell group consisting of a plurality of dummy cells connected incommon to a first dummy word line, and a second dummy cell groupconsisting of a plurality of dummy cells connected in common to a seconddummy word line, each of the dummy cells consisting of one transistorand one capacitor; and a switching transistor group consisting of aplurality of switching transistors each serving to erase data stored inan associated one of the dummy cells in response to a control signalexternally applied thereto; wherein respective capacitors of the dummycells are made of a dielectric film having no spontaneous polarizationcharacteristic; whereby when data is read out from an optional one ofthe unit cells on a selected one of the bit lines, a predeterminedvoltage outputted from that of dummy cells connected to an inverted bitline neighboring to the selected bit line is provided as a referencevoltage required for a comparison with a voltage corresponding to theread-out data.

In accordance with another aspect, the present invention provides aferroelectric random access memory comprising a plurality of bit linesextending in one direction, a plurality of word lines extending inanother direction perpendicular to the one direction, and a plurality ofunit cells arranged in an M×N array while being connected to associatedones of the lines, each of the unit cells consisting of one transistorand one capacitor, wherein the unit cells are grouped into a pluralityof unit cell groups, each of the unit cell groups consisting of aplurality of unit cells connected to associated ones of the bit lineswhile being connected to a plurality of word lines, respectively, insuch a fashion that they are arranged in an aligned fashion in a columndirection, those of the bit lines connected to each of the bit linesbeing connected together in series; further comprising: a dummy cellconnected to a dummy bit line and adapted to provide, to a selected oneof the bit lines, a reference voltage required for a data determinationwhen data is read out, the dummy cell consisting of one transistor andone capacitor; and a switching transistor serving to erase data storedin the dummy cell in response to a control signal externally appliedthereto; wherein the capacitor of the dummy cell is made of a dielectricfilm having no spontaneous polarization characteristic; whereby whendata is read out from an optional one of the unit cells on a selectedone of the bit lines, a predetermined voltage outputted from the dummycell connected to the dummy bit line is provided as a reference voltagerequired for a comparison with a voltage corresponding to the read-outdata.

The unit cells connected in common to a single word line may beconfigured to be connected in common to a single plate electrode line.Alternatively, respective plate electrodes of the unit cells may beconnected in common to a single plate electrode to which a predeterminedvoltage is applied.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects, and other features and advantages of the presentinvention will become more apparent after a reading of the followingdetailed description when taken in conjunction with the drawings, inwhich:

FIG. 1 is a hysteretic characteristic diagram illustrating polarizationcharacteristics of a ferroelectric film;

FIG. 2a is an equivalent circuit diagram illustrating a part of an FeRAMin accordance with a first embodiment of the present invention;

FIG. 2b is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a first modified embodiment from the first embodiment ofthe present invention;

FIG. 2c is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a second modified embodiment from the first embodiment ofthe present invention;

FIG. 3a is an equivalent circuit diagram illustrating a part of an FeRAMin accordance with a second embodiment of the present invention;

FIG. 3b is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a first modified embodiment from the second embodiment ofthe present invention;

FIG. 3c is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a second modified embodiment from the second embodiment ofthe present invention;

FIG. 3d is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a second modified embodiment from the third embodiment ofthe present invention;

FIG. 4a is an equivalent circuit diagram illustrating a part of an FeRAMin accordance with a third embodiment of the present invention;

FIG. 4b is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a second modified embodiment from the second embodiment ofthe present invention;

FIG. 4c is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a second modified embodiment from the third embodiment ofthe present invention;

FIG. 5 is an equivalent circuit diagram illustrating a part of an FeRAMin accordance with a fourth embodiment of the present invention;

FIG. 6 is a circuit diagram illustrating the equivalent circuit of aconventional FeRAM having a 1T/1C structure; and

FIG. 7 is a circuit diagram illustrating the equivalent circuit ofanother conventional FeRAM having a 2T/2C structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The important technical idea of the present invention is to provide thepresent invention provides an FeRAM which includes M×N unit cells, eachunit cell having a 1T/1C structure consisting of one transistor and onecapacitor, dummy cells provided for respective bit lines and adapted togenerate a reference voltage required for a data determination, andswitching transistors respectively corresponding to the dummy cells.Alternatively, a single dummy cell is used which is connected to aseparate dummy bit line. In accordance with the ON/OFF control of theswitching transistors corresponding to a selected dummy cell, thisselected dummy cell is used only when data is read out from anassociated unit cell. By virtue of such technical means, it is possibleto minimize the number of times using dummy cells for a generation ofthe reference voltage, thereby effectively preventing the number oftimes repeatedly using the FeRAM from being reduced, and to achieve ahigh integration of the FeRAM. Thus, the objects of the presentinvention can be easily accomplished.

Alternatively, a single plate electrode is used in common for memorycells, in place of plate electrode lines separated from one another in arow or column direction. By virtue of this configuration, it is possibleto accomplish the object of the present invention for achieving anincrease in capacitance within a given area.

Alternatively, the FeRAM has a configuration in which only one dummycell and one switching transistor are connected to a dummy bit line. Byvirtue of such a configuration, it is possible to achieve a highintegration of the memory while preventing the number of timesrepeatedly using the memory from being reduced.

Meanwhile, the FeRAM uses a capacitor having a ferroelectric film foreach unit cell while using a typical dielectric film having nospontaneous polarization characteristic while exhibiting a superiorresistance to a fatigue degradation over ferroelectric films havingspontaneous polarization characteristics, for the capacitors of dummycells. Accordingly, the dummy cells in the FeRAM of the presentinvention exhibit an enhanced reliability.

For the FeRAM according to the present invention, it is desirable to setthe capacitance of each dummy cell in such a fashion that itsubstantially corresponds to the capacitance of a ferroelectricexhibited in a residual polarization state. In particular, when the datastored in a unit cell selected for a data read procedure is “1”, thepotential variation dV1 on the bit line connected to the unit cellcorresponds to “dQ1/(Cb+Cs)” (dV1=dQ1/(Cb+Cs)). On the other hand, thedata stored in the unit cell is “0”, the potential variation dV0 on thebit line corresponds to “dQ0/(Cb+Cs)” (dV0=dQ0/(Cb+Cs)). Therefore, thepotential variation on an inverted bit line associated with the bit linecorresponds to “Qr/(Cb+Cs)”, which is approximately intermediate between“dV1” and “dV0”, by virtue of the capacitor of a dummy cell connected tothe inverted bit line.

Now, preferred embodiments of the present invention will be described indetail, in conjunction with the annexed drawings.

{First Embodiment}

FIG. 2a is an equivalent circuit diagram illustrating a part of an FeRAMin accordance with first embodiment of the present invention.

Referring to FIG. 2a, the FeRAM according to this embodiment includesM×N unit cells arranged in rows and columns in an interlaced fashion,like the black or white pattern of a chess plate. A plurality of unitcells arranged in the same row are connected together in series by oneof bit lines arranged in pair. The bit lines of each bit line pairoperate alternatingly in such a fashion that when data is read out onone bit line, the other bit line serves as an inverted bit lineproviding a reference voltage.

The FeRAM according to this embodiment extends in a row direction insuch a fashion that a plurality of unit cells are arranged in an M×Nmatrix array in which a plurality of word lines WL0 to WL3 eachconnected to a plurality of unit cells arranged in the same column crossa plurality of bit lines arranged in pair. Each bit line pair consistsof one bit line and one inverted bit line. In FIG. 2a, “BL0” and “BL1”denote the bit lines of one bit line pair, and “/BL0” and “/BL1” denotethe bit lines of another bit line pair. Respective plate electrodes ofthe unit cells are connected in common, so that a constant voltage isapplied to them.

Although the plate electrodes of the unit cells in this embodiment areillustrated as being connected in common by a single plate electrode PLso that a constant voltage is applied to them, plate electrode linesseparated in a column or row direction may be used in order toselectively apply a high voltage “Vcc” or a low voltage “0 V” to theplate electrode of each unit cell in accordance with data to be storedin that unit cell.

In particular, in the FeRAM according to this embodiment, each unit celldenoted by the reference character UC has a 1T/1C structure consistingof one transistor (a charge transfer transistor) and one capacitor. Adummy cell DC0, DC0′, DC1, or DC1′, which consists of one transistor (acharge transfer transistor) and one capacitor, is coupled to anassociated one of the bit lines BL0, BL0′, BL1, and BL1′ at one side ofthe associated bit line (the right side of FIG. 2a).

The transistor of each unit cell UC is coupled at a gate thereof to anassociated one of the word lines WL0, WL1, WL2, and WL3, at a drain (ora source) thereof to an associated one of the bit lines BL0, BL0′, BL1,and BL1′, and at a source (a drain) thereof to one end of the capacitorincluded in the unit cell UC. The other end of the capacitor isconnected to a single plate electrode line PL to which respective otherends of the capacitors in the remaining unit cells are connected incommon.

The transistors of the dummy cells DC0, DC0′, DC1, and DC1′ are coupledin common at their gates to a dummy word line DWL, and coupled at theirdrains (or sources) to the bit lines BL0, BL0′, BL1, and BL1′,respectively. The transistor of each dummy cell DC0, DC0′, DC1, or DC1′is also coupled at its source (or its drain) to one end of the capacitorincluded in the dummy cell. Respective other ends of the capacitors inthe dummy cells are connected in common.

A switching transistor is arranged on each bit line between the portionof the bit line, to which unit cells are coupled, and the portion of thebit line, to which an associated one of the dummy cells are coupled. Inthe illustrated case, a switching transistor ST0 is arranged on the bitline /BL0 between the portion of the bit line /BL0, to which the unitcells C10′ and C30′ are coupled, and the portion of the bit line /BL0,to which the dummy cell DC0′ is coupled. A switching transistor ST1 isarranged on the bit line /BL1 between the portion of the bit line /BL1,to which the unit cells C11′ and C31′ are coupled, and the portion ofthe bit line /BL1, to which the dummy cell DC1′ is coupled. A switchingtransistor ST2 is arranged on the bit line BL0 between the portion ofthe bit line BL0, to which the unit cells C00 and C20 are coupled, andthe portion of the bit line BL0, to which the dummy cell DC0 is coupled.A switching transistor ST3 is arranged on the bit line BL1 between theportion of the bit line BL1, to which the unit cells C01 and C21 arecoupled, and the portion of the bit line BL1 to which the dummy cell DC1is coupled.

The switching transistors ST0 and ST1 are coupled in common at theirgates to a control line CL0. The switching transistors ST2 and ST3 arecoupled in common at their gates to a control line CL1. When data is tobe stored or read out, a switching control signal from an external unitis applied to respective gates of the switching transistors ST0 to ST3.

Switching transistors ST4 to ST7 are coupled at their output terminalsto respective transistors of the dummy cells DC0, DC0′, DC1, and DC1′.When data is read out, the switching transistors ST0 to ST3 are turnedon or off in response to a switching control signal applied thereto viaa control line CLD, to which the switching transistors ST0 to ST3 areconnected in common, in order to clear data stored in the associateddummy cells, respectively.

As apparent from the above description, in the FeRAM according to thisembodiment, each unit cell has a 1T/1C structure consisting of onetransistor and one capacitor. In order to generate a reference voltagefor a determination of data read out on a bit line in this FeRAM, dummycells are used, which are respectively connected to bit linesneighboring to that bit line while having a potential inverse to thepotential of the bit line. In accordance with this configuration, dataread out from an optional unit cell is determined by applying, to acomparator C0 or C1, a voltage outputted from a bit line, on which thedata from that unit cell is read out, along with a reference voltageoutputted from bit lines neighboring to that bit line while having apotential inverse to the potential of the bit line, thereby comparingthe applied voltages. The dummy cells DC0, DC0′, DC1, and DC1′ connectedto respective bit lines are used only when data is read out from theassociated unit cells, respectively.

The procedures for storing data in the FeRAM having the above mentionedconfiguration according to this embodiment and reading out the storeddata will be described in detail.

For the convenience and best understanding of description, it is assumedin the following description that an application of a high voltage tothe bit line means the fact that the applied voltage is higher than thepotential of the plate electrode whereas an application of a low voltageto the bit line means the fact that the applied voltage is lower thanthe potential of the plate electrode. Also, it is assumed that thepotential variation of a bit line when output data is “1” corresponds to“V1”, and the potential variation of the bit line when output data is“0” corresponds to “V0”. Since the same data storing and readingprocedures are carried out in all unit cells, these procedures will bedescribed only in conjunction with the unit cells C00 and C10′.

First, the procedure for storing data “1” in the unit cell C00 will bedescribed. In order to store data, the dummy word line DWL and twocontrol lines CL0 and CL1 are switched to their OFF states,respectively. Also, the word line WL0 is switched to its ON state. Inthis state, a high voltage is applied to the bit line BL0. Due to apotential difference resulting from such a voltage application, theferroelectric film included in the unit cell C00 is polarized in a plus(+) direction. Accordingly, data “1” is stored.

Where it is desired to stored data “1” in the unit cell C10′, the wordline WL1 is switched to its ON state under the condition in which thecontrol lines CL0 and CL1 and dummy word line DLW are switched to theirOFF states, respectively. When a high voltage is applied to the bit line/BL0 in this state, the ferroelectric film included in the unit cellC10′ is polarized in a plus (+) direction due to a potential differenceresulting from the above mentioned voltage application. Accordingly,data “1” is stored.

Now, the procedure for storing data “0” in the unit cell C00 will bedescribed. In order to store data, the dummy word line DWL and twocontrol lines CL0 and CL1 are switched to their OFF states,respectively. Also, the word line WL0 is switched to its ON state. Inthis state, a low voltage is applied to the bit line BL0. Due to apotential difference resulting from such a voltage application, theferroelectric film included in the unit cell C00 is polarized in a minus(−) direction. Accordingly, data “0” is stored.

Where it is desired to store data “0” in the unit cell C10′, the wordline WL1 is switched to its ON state under the condition in which thecontrol lines CL0 and CL1 and dummy word line DWL are switched to theirOFF states, respectively. When a high voltage is applied to the bit line/BL0 in this state, the ferroelectric film included in the unit cellC10′ is polarized in a minus (−) direction due to a potential differenceresulting from the above mentioned voltage application. Accordingly,data “0” is stored.

As apparent from the above description, in the FeRAM according to thisembodiment, data “1” or data “0” is stored in respective unit cells C00and C10′ connected to the bit lines BL0 and /BL0 in accordance withvoltages (a high voltage or a low voltage) applied to those bit lines inaccordance with the above mentioned memory control procedures.

Although the control lines CL0 and CL1 and dummy word line DWL have beendescribed as being switched to their OFF states in the data storingprocedure according to this embodiment, they are not limited to such acondition. It is possible to obtain the same result even when thecontrol lines and dummy word line have a condition different from theabove mentioned condition, that is, they are switched to their ONstates.

As apparent from the above description, in the FeRAM according to thisembodiment, no dummy cell is used in the procedure for storing data inan optical unit cell. Accordingly, it is possible to considerably reducethe number of times using dummy cells. As a result, the number of timesrepeatedly using the FeRAM is relatively increased.

The procedure for reading out data “1” or “0” stored in the unit cellsC00 and C10′ in accordance with the above mentioned procedure will nowbe described.

First, the procedure for reading out data stored in the unit cell C00will be described. In this procedure, the control line CLD is firstswitched to its ON state so as to erase data stored in the dummy cells.After the data erasure, the control line CLD is switched again to itsOFF state. The control line CL1 is subsequently switched to its OFFstate. Also, the control line CL0 is switched to its ON state. In thisstate, a high voltage is applied to two bit lines BL0 and /BL0. Also,the word line WL0 and dummy word line DWL are switched to their ONstates, respectively. In this state, a potential variation of “V1” or“V0” occurs on the bit line BL0 in accordance with the data stored inthe unit cell C00. That is, where data “1” is stored in the unit cellC00, the potential variation of the bit line BL0 corresponds to “V1”. Onthe other hand, where data “0” is stored in the unit cell C00, thepotential variation of the bit line BL0 corresponds to “V0”.

At this time, the potential variation occurring on the inverted bit line/BL0 corresponds to a value approximately intermediate between “dV1” and“dV0” by virtue of the capacitor of the dummy cell DC0′. This potentialvariation is used as a reference voltage for a determination of dataread out from the unit cell C00.

That is, the voltage on the bit line BL0 and the reference voltage onthe inverted bit line /BL0 are transmitted to the comparator C0 which,in turn, determines the read-out data, based on the received voltages.When the voltage outputted from the bit line BL0 is higher than thereference voltage outputted from the inverted bit line /BL0, the dataread out from the unit cell C00 is determined to be data “1”. On theother hand, when the voltage outputted from the bit line BL0 is nothigher than the reference voltage outputted from the inverted bit line/BL0, the data read out from the unit cell C00 is determined to be data“0”.

In the procedure for reading out data stored in the unit cell C10′, thecontrol line CLD is first switched to its ON state so as to erase datastored in the dummy cells. After the data erasure, the control line CLDis switched again to its OFF state. The control line CL0 is subsequentlyswitched to its OFF state. Also, the control line CL1 is switched to itsON state. In this state, a high voltage is applied to two bit lines BL0and /BL0. Also, the word line WL1 and dummy word line DWL are switchedto their ON states, respectively. In this state, a potential variationof “V1” or “V0” occurs on the inverted bit line /BL0 in accordance withthe data stored in the unit cell C10′. That is, where data “1” is storedin the unit cell C10′, the potential variation of the bit line /BL0corresponds to “V1”. On the other hand, where data “0” is stored in theunit cell C10′, the potential variation of the bit line /BL0 correspondsto “V0”.

At this time, the potential variation occurring on the inverted bit lineBL0 corresponds to a value approximately intermediate between “dV1” and“dV0” by virtue of the capacitor of the dummy cell DC0. This potentialvariation is used as a reference voltage for a determination of dataread out from the unit cell C10′.

That is, the voltage on the bit line /BL0 and the reference voltage onthe inverted bit line BL0 are transmitted to the comparator C0 which, inturn, determines the read-out data, based on the received voltages. Whenthe voltage outputted from the bit line /BL0 is higher than thereference voltage outputted from the inverted bit line BL0, the dataread out from the unit cell C10′ is determined to be data “1”. On theother hand, when the voltage outputted from the bit line /BL0 is nothigher than the reference voltage outputted from the inverted bit lineBL0, the data read out from the unit cell C10′ is determined to be data“0”.

Thus, the FeRAM according to this embodiment uses no dummy cell in theprocedure for storing data an optional unit cell while using a dummycell in the procedure for reading out data from an optional unit cell.

As apparent from the above description, in an FeRAM according to thisembodiment, which consists of M×N unit cells, each unit cell having A1T/1C structure consisting of one transistor and one capacitor. In orderto generate a reference voltage for a determination of data read out ona bit line in the FeRAM, a dummy cells is used, which is connected to abit line (or an inverted bit line) neighboring to that bit line. Aswitching transistor is also provided which serves to erase data storedin an associated one of dummy cells connected to bit lines (or invertedbit lines) in response to a switching control signal applied therertovia a dummy word line. The FeRAM is also configured to use no dummy cellin the procedure for storing data an optional unit cell while using adesired dummy cell in the procedure for reading out data from anoptional unit cell. Accordingly, it is possible to effectively preventthe number of times repeatedly using the FeRAM from being reduced, andto achieve a high integration of the FeRAM.

Alternatively, a single plate electrode is used in common for memorycells, in place of separate plate electrode lines. By virtue of such aconfiguration, it is possible to achieve an increase in capacitancewithin a given area.

Although the capacitors of the dummy cells in the FeRAM according tothis embodiment may be formed using a separate capacitor fabricationprocess, it is more desirable to use gate capacitors which use a gateinsulating film as a dielectric film thereof. In this case, no separateprocess is required in the formation of the dummy cell capacitors.

FIG. 2b is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a first modified embodiment from the first embodiment ofthe present invention.

Referring to FIG. 2b, this first modified embodiment has the sameconfiguration and arrangement as those of the first embodiment, exceptthat the dummy cells DC0, DC0′, DC1, and DC1′ and switching transistorsST0 to ST7 are arranged at optional positions between unit cellsneighboring to each other in a row direction, respectively. For such anarrangement, each bit line, on which a plurality of unit cells areconnected, is divided into two separate portions. One dummy cell and oneswitching transistor are connected to one of the separate bit lineportions. The separate bit line portions of each bit line are connectedto each other by an interconnection line TCL0, /ICL0, ICL1, and /ICL1.

In the FeRAM according to the first modified embodiment, the proceduresfor inputting data to an optional unit cell, and reading out data storedin the optional unit cell are the same as those in the first embodiment.Accordingly, no further description will be made in conjunction withthose procedures.

This first modified embodiment illustrates the fact that the dummy cellsmay be arranged at optional positions between unit cells neighboring toeach other in a row direction, respectively.

Although the FeRAM according to the first modified embodiment hasslightly different configurations from those of the first embodiment inthat the dummy cells are arranged at optional positions between unitcells neighboring to each other in a row direction, respectively, thesame effect as that of the first embodiment can be obtained by dividingeach bit line into two separate portions, and appropriately connectingthe separate bit line portions by an interconnection line.

FIG. 2c is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a second modified embodiment from the first embodiment ofthe present invention.

Referring to FIG. 3c, this second modified embodiment has the sameconfiguration and arrangement as those of the first embodiment, exceptthat the unit cells of the same row connected in series on each of bitlines BL0, /BL0, BL1, and /BL1 are arranged in pair.

In the FeRAM according to this second modified embodiment, theprocedures for inputting data “1” or “0” to an optional unit cell, andreading out data stored in the optional unit cell are the same as thosein the second embodiment. Accordingly, no further description will bemade in conjunction with those procedures, in order to avoid anunnecessarily repeated description.

Although the FeRAM according to the second modified embodiment hasslightly different configurations from those of the first embodiment inthat the unit cells of the same row connected in series on each bit lineare arranged in pair, the same effect as that of the first embodimentcan be obtained.

{Second Embodiment}

FIG. 3a is an equivalent circuit diagram illustrating a part of an FeRAMin accordance with a second embodiment of the present invention.

Referring to FIG. 3a, the FeRAM according to this embodiment issubstantially identical to the first embodiment in terms of thearrangements of diverse lines including bit lines, word lines, dummyword line, and control lines, and unit cells, dummy cells, and switchingtransistors arranged in an interconnected fashion by those lines.However, the FeRAM according to this embodiment is different from thefirst embodiment in terms of the configurations and arrangements ofdummy cells and switching transistors.

That is, the FeRAM of this embodiment has a configuration in which onedummy cell and four switching transistors are provided for one bit linepair consisting of one bit line and one inverted bit line, as comparedto the FeRAM of the first embodiment in which one dummy cell and twoswitching transistors are provided for one bit line.

As shown in FIG. 3a, switching transistors ST0 to ST3 are arranged onthe bit lines BL0, /BL0, BL1, and /BL1, respectively. Those of theswitching transistors ST0 to ST3 arranged in an interlaced fashion in acolumn direction are coupled in common at gates thereof to a controlline CL0 or CL1. Switching transistors ST4 and ST5 are also connected incommon at gates thereof to a control line CL2. Each of the switchingtransistors ST4 and ST5 serves to connect together the bit lines of eachbit line pair, serving as complementary bit lines, that is, a bit lineand an inverted bit line. Dummy cells DC0 and DC1, which are connectedat gates thereof in common to a dummy word line DWL, are provided forrespective bit line pairs. Each dummy cell is connected to one of thebit lines included in the associated bit line pair. Switchingtransistors ST6 and ST7 are also provided which are connected at gatesthereof in common to a control line CLD. Each of the switchingtransistors ST6 and ST7 is connected between one end of an associatedone of the dummy cells DC0 and DC1 and the ground.

In order to avoid an unnecessarily repeated description for the secondembodiment, no description will be made in conjunction with the wholearrangement of the FeRAM according to this embodiment. In the followingdescription, only the procedure for storing data in the FeRAM accordingto this embodiment using the common plate electrode line, and readingout the stored data will be described.

For the convenience and best understanding of description, it is assumedin the following description that an application of a high voltage tothe bit line means the fact that the applied voltage is higher than thepotential of the plate electrode whereas an application of a low voltageto the bit line means the fact that the applied voltage is lower thanthe potential of the plate electrode. Also, it is assumed that thepotential variation of a bit line when output data is “1” corresponds to“V1”, and the potential variation of the bit line when output data is“0” corresponds to “V0”.

Since the same data storing and reading procedures are carried out inthe all unit cells, these procedures will be described only inconjunction with the unit cells C00 and C10′.

Furthermore, the procedures for storing data in respective unit cellsC00 and C10′ are the same as those in the first embodiment. In thefollowing description, accordingly, only the procedures for reading outdata stored in respective unit cells C00 and C10′ will be described inorder to avoid an unnecessarily repeated description.

First, the procedure for reading out data stored in the unit cell C00will be described. In this procedure, the control line CLD is firstswitched to its ON state so as to erase data stored in the dummy cells.After the data erasure, the control line CLD is switched again to itsOFF state. The control line CL1 is subsequently switched to its OFFstate. Also, the control lines CL0 and CL2 are switched to their ONstates. In this state, a high voltage is applied to two bit lines BL0and /BL0. Also, the word line WL0 and dummy word line DWL are switchedto their ON states, respectively. In this state, a potential variationof “V1” or “V0” occurs on the bit line BL0 in accordance with the datastored in the unit cell C00. That is, where data “1” is stored in theunit cell C00, the potential variation of the bit line BL0 correspondsto “V1”. On the other hand, where data “0” is stored in the unit cellC00, the potential variation of the bit line BL0 corresponds to “V0”.

At this time, the potential variation occurring on the inverted bit line/BL0 corresponds to a value approximately intermediate between “dV1” and“dV0” by virtue of the capacitor of the dummy cell DC0′. This potentialvariation is used as a reference voltage for a determination of dataread out from the unit cell C00.

That is, the voltage on the bit line BL0 and the reference voltage onthe inverted bit line /BL0 are transmitted to the comparator C0 which,in turn, determines the read-out data, based on the received voltages.When the voltage outputted from the bit line BL0 is higher than thereference voltage outputted from the inverted bit line /BL0, the dataread out from the unit cell C00 is determined to be data “1”. On theother hand, when the voltage outputted from the bit line BL0 is nothigher than the reference voltage outputted from the inverted bit line/BL0, the data read out from the unit cell C00 is determined to be data“0”.

In the procedure for reading out data stored in the unit cell C10′, thecontrol line CLD is first switched to its ON state so as to erase datastored in the dummy cells. After the data erasure, the control line CLDis switched again to its OFF state. The control line CL0 is subsequentlyswitched to its OFF state. Also, the control line CL1 is switched to itsON state. In this state, a high voltage is applied to two bit lines BL0and /BL0. Also, the word line WL1 and dummy word line DWL are switchedto their ON states, respectively. In this state, a potential variationof “V1” or “V0” occurs on the inverted bit line /BL0 in accordance withthe data stored in the unit cell C10′. That is, where data “1” is storedin the unit cell C10′, the potential variation of the bit line /BL0corresponds to “V1”. On the other hand, where data “0” is stored in theunit cell C10′, the potential variation of the bit line /BL0 correspondsto “V0”.

At this time, the potential variation occurring on the inverted bit lineBL0 corresponds to a value approximately intermediate between “dV1” and“dV0” by virtue of the capacitor of the dummy cell DC0. This potentialvariation is used as a reference voltage for a determination of dataread out from the unit cell C10′.

That is, the voltage on the bit line /BL0 and the reference voltage onthe inverted bit line BL0 are transmitted to the comparator C0 which, inturn, determines the read-out data, based on the received voltages. Whenthe voltage outputted from the bit line /BL0 is higher than thereference voltage outputted from the inverted bit line BL0, the dataread out from the unit cell C10′ is determined to be data “1”. On theother hand, when the voltage outputted from the bit line /BL0 is nothigher than the reference voltage outputted from the inverted bit lineBL0, the data read out from the unit cell C10′ is determined to be data“0”.

Thus, the FeRAM according to this embodiment uses no dummy cell in theprocedure for storing data an optional unit cell while using a dummycell in the procedure for reading out data from an optional unit cell,as in the first embodiment.

As apparent from the above description, the FeRAM according to thisembodiment uses no dummy cell in the procedure for storing data anoptional unit cell. In the procedure for reading out data from anoptional unit cell, a dummy cell is used which is connected to theinverted bit line associated with the unit cell. Accordingly, the sameresult as that of the first embodiment is obtained. That is, it ispossible to effectively prevent the number of times repeatedly using theFeRAM from being reduced due to an excessive use of dummy cells, and toachieve a high integration of the FeRAM.

Alternatively, a single plate electrode is used in common for memorycells, in place of separate plate electrode lines. By virtue of such aconfiguration, it is possible to achieve an increase in capacitancewithin a given area.

In accordance with this embodiment, the capacitors of the dummy cellsmay be formed using a separate capacitor fabrication process.Alternatively, gate capacitors may be used which use a gate insulatingfilm as a dielectric film thereof.

FIG. 3b is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a first modified embodiment from the second embodiment ofthe present invention.

Referring to FIG. 3b, this first modified embodiment has the sameconfiguration and arrangement as those of the second embodiment, exceptthat the dummy cells DC0, DC0′, DC1, and DC1′ and switching transistorsST0 to ST7 are arranged at optional positions between unit cellsneighboring to each other in a row direction, respectively. For such anarrangement, each bit line, on which a plurality of unit cells areconnected, is divided into two separate portions. One dummy cell and oneswitching transistor are connected to one of the separate bit lineportions. The separate bit line portions of each bit line are connectedto each other by an interconnection line ICL0, /ICL0, ICL1, and /ICL1.

In the FeRAM according to the first modified embodiment, the proceduresfor inputting data to an optional unit cell, and reading out data storedin the optional unit cell are the same as those in the first embodiment.Accordingly, no further description will be made in conjunction withthose procedures.

This first modified embodiment illustrates the fact that the dummy cellsmay be arranged at optional positions between unit cells neighboring toeach other in a row direction, respectively.

Although the FeRAM according to the first modified embodiment hasslightly different configurations from those of the second embodiment inthat the dummy cells are arranged at optional positions between unitcells neighboring to each other in a row direction, respectively, thesame effect as that of the first embodiment can be obtained by dividingeach bit line into two separate portions, and appropriately connectingthe separate bit line portions by an interconnection line.

FIG. 3c is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a second modified embodiment from the second embodiment ofthe present invention.

Referring to FIG. 3c, this second modified embodiment has the sameconfiguration and arrangement as those of the second embodiment, exceptthat one dummy cell is provided for every four bit lines, as compared tothe first embodiment in which one dummy cell is provided for every twobit lines. In order to avoid an unnecessarily repeated description forthis second modified embodiment, therefore, a description will be madeonly in conjunction with the configuration of this embodiment differentfrom the first modified one of the second embodiment.

As mentioned above, the FeRAM according to this second modifiedembodiment has a configuration in which one dummy cell is provided forevery four bit lines. For this configuration, the FeRAM includesswitching transistors ST0 to ST3 respectively arranged on the bit linesBL0, /BL0, BL1, and /BL1. Those of the switching transistors ST0 to ST3arranged in an interlaced fashion in a column direction are coupled incommon at gates thereof to a control line CL0 or CL1. The FeRAM alsoincludes a switching transistor ST4 connected at a gate thereof to acontrol line CL2 and adapted to connect a reference bit line, forexample, “BL0”, with the bit line /BL0 neighboring to the reference bitline BL0, a switching transistor ST5 connected at a gate thereof to acontrol line CL3 and adapted to connect the reference bit line BL0 withthe bit line BL1 neighboring to the reference bit line BL0 while beingspaced from the reference bit line BL0 by one row, and a switchingtransistor ST6 connected at a gate thereof to a control line CL4 andadapted to connect the reference bit line BL0 with the bit line /BL1neighboring to the reference bit line BL0 while being spaced from thereference bit line BL0 by two rows.

In the FeRAM according to the second modified embodiment, the proceduresfor inputting data to an optional unit cell, and reading out data storedin the optional unit cell are the same as those in the secondembodiment. Accordingly, no further description will be made inconjunction with those procedures.

This second modified embodiment illustrates the fact that one dummy cellmay be provided for every desired number of bit lines.

Although the FeRAM according to the second modified embodiment hasslightly different configurations from those of the second embodiment inthat one dummy cell is provided for every four bit lines, the sameeffect as that of the first embodiment can be obtained.

FIG. 3d is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a third modified embodiment from the second embodiment ofthe present invention.

Referring to FIG. 3d, this third modified embodiment has the sameconfiguration and arrangement as those of the second embodiment, exceptthat the unit cells of the same row connected in series on each of bitlines BL0, /BL0, BL1, and /BL1 are arranged in pair.

In the FeRAM according to this third modified embodiment, the proceduresfor inputting data “1” or “0” to an optional unit cell, and reading outdata stored in the optional unit cell are the same as those in thesecond embodiment. Accordingly, no further description will be made inconjunction with those procedures, in order to avoid an unnecessarilyrepeated description.

Although the FeRAM according to the third modified embodiment hasslightly different configurations from those of the first embodiment inthat the unit cells of the same row connected in series on each bit lineare arranged in pair, the same effect as that of the second embodimentcan be obtained.

[Third Embodiment]

FIG. 4a is an equivalent circuit diagram illustrating a part of an FeRAMin accordance with a third embodiment of the present invention.

Referring to FIG. 4a, the FeRAM according to this embodiment isidentical to the above mentioned first embodiment of the presentinvention, in terms of the arrangements of diverse lines including bitlines, word lines, dummy word line, and control lines, and thearrangement in which switching transistors ST0 to ST3 are connected torespective dummy cells connected to bit lines BL0, /BL0, BL1, and /BL1.

However, the FeRAM according to this embodiment is different from thefirst embodiment in terms of the configurations and arrangements ofdummy cells and switching transistors. That is, in this embodiment, thedummy cells have the same arrangement as that of the unit cells. Inorder to implement such configurations and arrangements according tothis embodiment, two dummy word lines DWL0 and DWL1 are used in such afashion that one of the dummy word lines, that is, the dummy word lineDWL1, is associated with the dummy cells DC0 and DC1 respectivelyconnected to the bit lines BL0 and BL1 (or the inverted bit lines) inodd rows (or even rows) whereas the other dummy word line, that is, thedummy word line DWL2, is associated with the dummy cells DC0′ and DC1′respectively connected to the bit lines /BL0 and /BL1 (or the invertedbit lines) in even rows (or odd rows).

In the illustrated case, a single control line CLD is used to erase datastored in all dummy cells. However, two separate control lines may beused to control the dummy cells, as in the dummy word lines.

As apparent from the above description, the FeRAM according to thisembodiment has an arrangement in which one dummy cell and one switchingtransistor are used for every bit line, as compared to the FeRAM of thefirst embodiment in which one dummy cell and two switching transistorsare used for every bit line.

In order to avoid an unnecessarily repeated description for the thirdembodiment, no description will be made in conjunction with the wholearrangement of the FeRAM according to this embodiment. In the followingdescription, only the procedure for storing data in the FeRAM accordingto this embodiment using a simplified switching transistor arrangement,and reading out the stored data will be described.

For the convenience and best understanding of description, it is assumedin the following description that an application of a high voltage tothe bit line means the fact that the applied voltage is higher than thepotential of the plate electrode whereas an application of a low voltageto the bit line means the fact that the applied voltage is lower thanthe potential of the plate electrode. Also, it is assumed that thepotential variation of a bit line when output data is “1” corresponds to“V1”, and the potential variation of the bit line when output data is“0” corresponds to “V0”.

Since the same data storing and reading procedures are carried out inall unit cells, these procedures will be described only in conjunctionwith the unit cells C00 and C10′.

First, the procedure for storing data “1” in the unit cell C00 will bedescribed. In order to store data, the word line WL0 is switched to itsON state. In this state, a high voltage is applied to the bit line BL0.Due to a potential difference resulting from such a voltage application,the ferroelectric film included in the unit cell C00 is polarized in aplus (+) direction. Accordingly, data “1” is stored.

Where it is desired to store data “1” in the unit cell C10′, the wordline WL1 is switched to its ON state. When a high voltage is applied tothe bit line /BL0 in this state, the ferroelectric film included in theunit cell C10′ is polarized in a plus (+) direction due to a potentialdifference resulting from the above mentioned voltage application.Accordingly, data “1” is stored.

Now, the procedure for storing data “0” in the unit cell C00 will bedescribed. In order to store data, the word line WL0 is switched to itsON state. In this state, a low voltage is applied to the bit line BL0.Due to a potential difference resulting from such a voltage application,the ferroelectric film included in the unit cell C00 is polarized in aminus (−) direction. Accordingly, data “0” is stored.

Where it is desired to store data “0” in the unit cell C10′, the wordline WL1 is switched to its ON state. When a high voltage is applied tothe bit line /BL0 in this state, the ferroelectric film included in theunit cell C10′ is polarized in a minus (−) direction due to a potentialdifference resulting from the above mentioned voltage application.Accordingly, data “0” is stored.

As apparent from the above description, in the FeRAM according to thisembodiment, data “1” or data “0” is stored in respective unit cells C00and C10′ connected to the bit lines BL0 and /BL0 in accordance withvoltages (a high voltage or a low voltage) applied to those bit lines inaccordance with the above mentioned memory control procedures.

As apparent from the above description, in the FeRAM according to thisembodiment, no dummy cell is used in the procedure for storing data inan optional unit cell. Accordingly, it is possible to considerablyreduce the number of times using dummy cells. As a result, the number oftimes repeatedly using the FeRAM is relatively increased.

The procedure for reading out data “1” or “0” stored in the unit cellsC00 and C10′ in accordance with the above mentioned procedure will nowbe described.

First, the procedure for reading out data stored in the unit cell C00will be described. In this procedure, the control line CLD is firstswitched to its ON state so as to erase data stored in the dummy cells.After the data erasure, the control line CLD is switched again to itsOFF state. In this state, a high voltage is applied to two bit lines BL0and /BL0. Also, the word line WL0 and the dummy word line DWL areswitched to their ON states, respectively. In this state, a potentialvariation of “V1” or “V0” occurs on the bit line BL0 in accordance withthe data stored in the unit cell C00. That is, where data “1” is storedin the unit cell C00, the potential variation of the bit line BL0corresponds to “V1”. On the other hand, where data “0” is stored in theunit cell C00, the potential variation of the bit line BL0 correspondsto “V0”.

At this time, the potential variation occurring on the inverted bit line/BL0 corresponds to a value approximately intermediate between “dV1” and“dV0” by virtue of the capacitor of the dummy cell DC0′. This potentialvariation is used as a reference voltage for a determination of dataread out from the unit cell C00.

That is, the voltage on the bit line BL0 and the reference voltage onthe inverted bit line /BL0 are transmitted to the comparator C0 which,in turn, determines the read-out data, based on the received voltages.When the voltage outputted from the bit line BL0 is higher than thereference voltage outputted from the inverted bit line /BL0, the dataread out from the unit cell C00 is determined to be data “1”. On theother hand, when the voltage outputted from the bit line BL0 is nothigher than the reference voltage outputted from the inverted bit line/BL0, the data read out from the unit cell C00 is determined to be data“0”.

In the procedure for reading out data stored in the unit cell C10′, thecontrol line CLD is first switched to its ON state so as to erase datastored in the dummy cells. After the data erasure, the control line CLDis switched again to its OFF state. In this state, a high voltage isapplied to two bit lines BL0 and /BL0. Also, the word line WL1 and dummyword line DWL are switched to their ON states, respectively. In thisstate, a potential variation of “V1” or “V0” occurs on the bit line /BL0in accordance with the data stored in the unit cell C10′. That is, wheredata “1” is stored in the unit cell C10′, the potential variation of thebit line /BL0 corresponds to “V1”. On the other hand, where data “0” isstored in the unit cell C10′, the potential variation of the bit line/BL0 corresponds to “V0”.

At this time, the potential variation occurring on the inverted bit lineBL0 corresponds to a value approximately intermediate between “dV1” and“dV0” by virtue of the capacitor of the dummy cell DC0. This potentialvariation is used as a reference voltage for a determination of dataread out from the unit cell C10′.

That is, the voltage on the bit line /BL0 and the reference voltage onthe inverted bit line BL0 are transmitted to the comparator C0 which, inturn, determines the read-out data, based on the received voltages. Whenthe voltage outputted from the bit line /BL0 is higher than thereference voltage outputted from the inverted bit line BL0, the dataread out from the unit cell C10′ is determined to be data “1”. On theother hand, when the voltage outputted from the bit line /BL0 is nothigher than the reference voltage outputted from the inverted bit lineBL0, the data read out from the unit cell C10′ is determined to be data“0”.

Thus, the FeRAM according to this embodiment uses no dummy cell in theprocedure for storing data an optional unit cell while using a dummycell in the procedure for reading out data from an optional unit cell.

As apparent from the above description, the FeRAM according to thisembodiment obtains the same effects as those of the first embodimentbecause the FeRAM is configured to use no dummy cell in the procedurefor storing data an optional unit cell while using a dummy cellassociated with a unit cell in the procedure for reading out data fromthe unit cell. That is, it is possible to effectively prevent the numberof times repeatedly using the FeRAM from being reduced, and to achieve ahigh integration of the FeRAM.

Alternatively, a single plate electrode is used in common for memorycells, in place of separate plate electrode lines, as in the firstembodiment. By virtue of such a configuration, it is possible to achievean increase in capacitance within a given area.

In accordance with this embodiment, the capacitors of the dummy cellsmay be formed using a separate capacitor fabrication process.Alternatively, gate capacitors may be used which use a gate insulatingfilm as a dielectric film thereof.

FIG. 4b is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a first modified one of the third embodiment of the presentinvention.

Referring to FIG. 4b, this first modified embodiment has the sameconfiguration and arrangement as those of the third embodiment, exceptthat the dummy cells DC0, DC0′, DC1, and DC1′ and switching transistorsST0 to ST3 are arranged at optional positions between unit cellsneighboring to each other in a row direction, respectively.

In the FeRAM according to the first modified embodiment, the proceduresfor inputting data to an optional unit cell, and reading out data storedin the optional unit cell are the same as those in the first embodiment.Accordingly, no further description will be made in conjunction withthose procedures.

This first modified embodiment illustrates the fact that the dummy cellsmay be arranged at optional positions between unit cells neighboring toeach other in a row direction, respectively.

Although the FeRAM according to the first modified embodiment hasslightly different configurations from those of the third embodiment inthat the dummy cells are arranged at optional positions between unitcells neighboring to each other in a row direction, respectively, thesame effect as that of the first embodiment can be obtained.

FIG. 4c is an equivalent circuit diagram illustrating a part of an FeRAMaccording to a second modified one of the third embodiment of thepresent invention.

Referring to FIG. 4c, this second modified embodiment has the sameconfiguration and arrangement as those of the third embodiment, exceptthat the unit cells of the same row connected in series on each of bitlines BL0, /BL0, BL1, and /BL1 are arranged in pair.

In the FeRAM according to this second modified embodiment, theprocedures for inputting data “1” or “0” to an optional unit cell, andreading out data stored in the optional unit cell are the same as thosein the third embodiment. Accordingly, no further description will bemade in conjunction with those procedures, in order to avoid anunnecessarily repeated description.

Although the FeRAM according to the second modified embodiment hasslightly different configurations from those of the third embodiment inthat the unit cells of the same row connected in series on each bit lineare arranged in pair, the same effect as that of the first embodimentcan be obtained.

[Fourth Embodiment]

FIG. 5 is an equivalent circuit diagram illustrating a part of an FeRAMin accordance with a fourth embodiment of the present invention.

Referring to FIG. 5, the FeRAM according to this embodiment is differentfrom those of the first through third embodiments in which in theprocedure for reading out data stored in an unit cell, the dummy cellconnected to the bit line neighboring to the bit line, on which data isread out, is used to generate a reference voltage required for adetermination of the read data. That is, in the FeRAM according to thisembodiment, a single dummy cell DC is used to generate a referencevoltage. The dummy cell DC is connected to a separate dummy bit lineDBL. The dummy cell DC is also connected in parallel to a plurality ofcomparators C0 and C1.

This FeRAM of the fourth embodiment is slightly similar to theconventional FeRAM of FIG. 6 in that a single dummy cell DC is connectedto a separate dummy bit line DBL. However, the FeRAM of this embodimentis apparently different from the conventional FeRAM of FIG. 6 in that itincludes a single dummy cell DC and a single switching transistor, andthat the dummy cell is not used in the procedure for storing data in anoptional unit cell, but used only in the procedure for reading out datafrom an optional unit cell.

The procedures for storing data in respective unit cells C00 and C10′are the same as those in the above mentioned embodiments. In thefollowing description, accordingly, only the procedures for reading outdata stored in respective unit cells C00 and C01 will be described inorder to avoid an unnecessarily repeated description.

First, the procedure for reading out data stored in the unit cell C00will be described. In this procedure, the control line CLD is firstswitched to its ON state so as to erase data stored in the dummy cells.After the data erasure, the control line CLD is switched again to itsOFF state. In this state, a high voltage is applied to the bit line BL0and the dummy bit line DBL. Also, the word line WL0 and dummy word lineDWL are switched to their ON states, respectively. In this state, apotential variation of “V1” or “V0” occurs on the bit line BL0 inaccordance with the data stored in the unit cell C00. That is, wheredata “1” is stored in the unit cell C00, the potential variation of thebit line BL0 corresponds to “V1”. On the other hand, where data “0” isstored in the unit cell C00, the potential variation of the bit line BL0corresponds to “V0”.

At this time, the potential variation occurring on the dummy bit lineDBL corresponds to a value approximately intermediate between “dV1” and“dV0” by virtue of the capacitor of the dummy cell DC0′. This potentialvariation is used as a reference voltage for a determination of dataread out from the unit cell C00.

That is, the voltage on the bit line BL0 and the reference voltage onthe dummy bit line DBL are transmitted to the comparator C0 which, inturn, determines the read-out data, based on the received voltages. Whenthe voltage outputted from the bit line BL0 is higher than the referencevoltage outputted from the dummy bit line DBL, the data read out fromthe unit cell C00 is determined to be data “1”. On the other hand, whenthe voltage outputted from the bit line BL0 is not higher than thereference voltage outputted from the dummy bit line DBL, the data readout from the unit cell C00 is determined to be data “0”.

In the procedure for reading out data stored in the unit cell C01, thecontrol line CLD is first switched to its ON state so as to erase datastored in the dummy cells. After the data erasure, the control line CLDis switched again to its OFF state. In this state, a high voltage isapplied to the bit line BL1 and dummy bit line DBL. Also, the word lineWL0 and dummy word line DWL are switched to their ON states,respectively. In this state, a potential variation of “V1” or “V0”occurs on the bit line BL1 in accordance with the data stored in theunit cell C01. That is, where data “1” is stored in the unit cell C01,the potential variation of the bit line BL1 corresponds to “V1”. On theother hand, where data “0” is stored in the unit cell C01, the potentialvariation of the bit line BL1 corresponds to “V0”.

At this time, the potential variation occurring on the dummy bit lineDBL corresponds to a value approximately intermediate between “dV1” and“dV0” by virtue of the capacitor of the dummy cell DC. This potentialvariation is used as a reference voltage for a determination of dataread out from the unit cell C01.

That is, the voltage on the bit line BL1 and the reference voltage onthe dummy bit line DBL are transmitted to the comparator C0 which, inturn, determines the read-out data, based on the received voltages. Whenthe voltage outputted from the bit line BL1 is higher than the referencevoltage outputted from the dummy bit line DBL, the data read out fromthe unit cell C01 is determined to be data “1”. On the other hand, whenthe voltage outputted from the bit line BL1 is not higher than thereference voltage outputted from the dummy bit line DBL, the data readout from the unit cell C01 is determined to be data “0”.

Thus, the FeRAM according to this embodiment uses no dummy cell in theprocedure for storing data an optional unit cell while using a dummycell in the procedure for reading out data from an optional unit cell.

As apparent from the above description, the FeRAM according to thisembodiment obtains the same effects as those of the first embodimentbecause the FeRAM is configured to use no dummy cell in the procedurefor storing data an optional unit cell while using a dummy cellassociated with a unit cell in the procedure for reading out data fromthe unit cell. That is, it is possible to effectively prevent the numberof times repeatedly using the FeRAM from being reduced, and to achieve ahigh integration of the FeRAM.

Alternatively, a single plate electrode is used in common for memorycells, in place of separate plate electrode lines, as in the firstembodiment. By virtue of such a configuration, it is possible to achievean increase in capacitance within a given area.

In accordance with this embodiment, the capacitors of the dummy cellsmay be formed using a separate capacitor fabrication process.Alternatively, gate capacitors may be used which use a gate insulatingfilm as a dielectric film thereof.

As apparent from the above description, the present invention providesan FeRAM which includes M×N unit cells, each unit cell having a 1T/1Cstructure consisting of one transistor and one capacitor, dummy cellsprovided for respective bit lines and adapted to generate a referencevoltage required for a data determination, and switching transistorsrespectively corresponding to the dummy cells. Alternatively, a singledummy cell is used which is connected to a separate dummy bit line. Inaccordance with the ON/OFF control of the switching transistorscorresponding to a selected dummy cell, this selected dummy cell is usedonly when data is read out from an associated unit cell. Accordingly, itis possible to minimize the number of times using dummy cells for ageneration of the reference voltage, thereby effectively preventing thenumber of times repeatedly using the FeRAM from being reduced, and toachieve a high integration of the FeRAM.

Alternatively, a single plate electrode is used in common for memorycells, in place of plate electrode lines separated from one another in arow or column direction. By virtue of such a configuration, it ispossible to achieve an increase in capacitance within a given area. Aferroelectric film is used for the capacitor of each unit cell, and atypical dielectric film exhibiting a superior resistance to a fatiguedegradation over the ferroelectric film is used for the capacitor ofeach dummy cell. Accordingly, it is possible to achieve an enhancedreliability of the dummy cells.

Although the preferred embodiments of the invention have been disclosedfor illustrative purposes, those skilled in the art will appreciate thatvarious modification, additions and substitutions are possible, withoutdeparting from the scope and spirit of the invention as disclosed in theaccompanying claims.

What is claimed is:
 1. A ferroelectric random access memory comprising aplurality of bit lines extending in one direction, a plurality of wordlines extending in another direction perpendicular to the one direction,and a plurality of unit cells arranged in an M×N array while beingconnected to associated ones of the lines, each of the unit cellsconsisting of one transistor and one capacitor, wherein the unit cellsare grouped into a plurality of unit cell groups, each of the unit cellgroups consisting of a plurality of unit cells connected to associatedones of the bit lines, respectively, in such a fashion that they arearranged in an interlaced fashion in a row direction or in a columndirection, those of the bit lines connected to each of the bit linesbeing connected together in series; further comprising: a dummy cellgroup consisting of a plurality of dummy cells each connected to anassociated one of the bit lines at an optional position on theassociated bit line, each of the dummy cells consisting of onetransistor and one capacitor; a first switching transistor groupconsisting of a plurality of switching transistors each serving toswitch a connection among associated ones of the unit cells on one ofthe bit lines corresponding to an associated one of the dummy cells inresponse to a control signal externally applied thereto; and a secondswitching transistor group consisting of a plurality of switchingtransistors each serving to erase data stored in an associated one ofthe dummy cells in response to a control signal externally appliedthereto; wherein respective capacitors of the dummy cells are made of adielectric film having no spontaneous polarization characteristic;whereby when data is read out from an optional one of the unit cells ona selected one of the bit lines, a predetermined voltage outputted fromthat of dummy cells connected to an inverted bit line neighboring to theselected bit line is provided as a reference voltage required for acomparison with a voltage corresponding to the read-out data.
 2. Theferroelectric random access memory according to claim 1, wherein thedummy cell groups and the first and second switching transistor groupsare arranged at optional positions within a selected one of the unitcell groups, respectively, in such a fashion that they separate each ofthe bit lines into two portions, the separated bit line portions beingconnected by an interconnection line.
 3. The ferroelectric random accessmemory according to claim 2, wherein respective plate electrodes of theunit cells are connected to plate electrode lines spaced from oneanother in a row direction in such a fashion that one of unit cellgroups each consisting of N unit cells is connected to an associated oneof the plate electrode lines.
 4. The ferroelectric random access memoryaccording to claim 2, wherein respective plate electrodes of the unitcells are connected in common by a plate electrode line.
 5. Theferroelectric random access memory according to claim 2, whereinrespective plate electrodes of the dummy cells are connected to theground.
 6. The ferroelectric random access memory according to claim 2,wherein a predetermined voltage is applied to respective plateelectrodes of the dummy cells.
 7. The ferroelectric random access memoryaccording to claim 2, wherein two unit cells are arranged in pair oneach of the bit lines in such a fashion that they are connected togetherin series, and the unit cell pairs are arranged in an alternatingfashion between neighboring ones of the bit lines.
 8. The ferroelectricrandom access memory according to claim 2, wherein the bit lines arearranged in pair to form bit line pairs each consisting of two bitlines, the dummy cells connected to respective one-side bit lines of thebit line pairs are connected in common to a dummy word line, and thedummy cells connected to respective other-side bit lines of the bit linepairs are connected in common to another dummy word line.
 9. Theferroelectric random access memory according to claim 2, whereinrespective capacitors of the unit cells are made of a ferroelectricfilm, and respective capacitors of the dummy cells are made of adielectric film.
 10. The ferroelectric random access memory according toclaim 9, wherein the capacitor of each dummy cell is a gate capacitorusing a dielectric film as a gate insulating film thereof.
 11. Theferroelectric random access memory according to claim 2, wherein thefirst switching transistor group comprises: a first switching groupconsisting of a plurality of switching transistors respectively arrangedon those of the bit lines corresponding to one of two interlaced bitline groups each consisting of interlaced bit lines, each of theswitching transistors in the first switching group serving to switch aconnection of the dummy cell, arranged on an associated one of the bitlines in the one interlaced bit line group, to the associated bit line,the switching transistors in the first switching group being connectedin common to a first control line; and a second switching groupconsisting of a plurality of switching transistors respectively arrangedon those of the bit lines corresponding to the other one of theinterlaced bit line groups, each of the switching transistors in thesecond switching group serving to switch a connection of the dummy cell,arranged on an associated one of the bit lines in the other interlacedbit line group, to the associated bit line, the switching transistors inthe second switching group being connected in common to a second controlline.
 12. The ferroelectric random access memory according to claim 11,wherein when data is stored in an optional one of the unit cells, thefirst and second switching groups are controlled to be switched to OFFstates thereof in response to a switching control signal externallyapplied thereto, respectively.
 13. The ferroelectric random accessmemory according to claim 11, wherein when data is read out from anoptional one of the unit cells, the first and second switching groupsare controlled in such a fashion that one of the first and secondswitching groups is switched to an ON state thereof in response to aswitching control signal externally applied thereto whereas the otherone of the first and second switching groups is switched to an OFF statethereof in response to a switching control signal externally appliedthereto.
 14. A ferroelectric random access memory comprising a pluralityof bit lines extending in one direction, a plurality of word linesextending in another direction perpendicular to the one direction, and aplurality of unit cells arranged in an M×N array while being connectedto associated ones of the lines, each of the unit cells consisting ofone transistor and one capacitor, wherein the unit cells are groupedinto a plurality of unit cell groups, each of the unit cell groupsconsisting of a plurality of unit cells connected to associated ones ofthe bit lines, respectively, in such a fashion that they are arranged inan interlaced fashion in a row direction or in a column direction, thoseof the bit lines connected to each of the bit lines being connectedtogether in series; wherein the bit lines are arranged in pair, each ofthe bit line pairs consisting of two bit lines; further comprising: adummy cell group consisting of a plurality of dummy cells each connectedto one of bit lines included in an associated one of the bit line pairsat an optional position on the bit line, each of the dummy cellsconsisting of one transistor and one capacitor; a first switchingtransistor group consisting of a plurality of switching transistors eachserving to switch a connection among the unit cells on one bit lineincluded in an associated one of the bit line pairs respectivelycorresponding to the dummy cells in response to a control signalexternally applied thereto; a second switching transistor groupconsisting of a plurality of switching transistors each serving toswitch a connection between the bit lines included in an associated oneof the bit line pairs respectively corresponding to the dummy cells inresponse to a control signal externally applied thereto, the switchingtransistors of the second switching transistor group corresponding innumber to the dummy cells; and a third switching transistor groupconsisting of a plurality of switching transistors each serving to erasedata stored in an associated one of the dummy cells in response to acontrol signal externally applied thereto; wherein respective capacitorsof the dummy cells are made of a dielectric film having no spontaneouspolarization characteristic; whereby when data is read out from anoptional one of the unit cells on a selected one of the bit lines, apredetermined voltage outputted from that of dummy cells connected tothe bit line pair including the selected bit line is provided pair as areference voltage required for a comparison with a voltage correspondingto the read-out data.
 15. The ferroelectric random access memoryaccording to claim 14, wherein the dummy cell groups and the firstthrough third switching transistor groups are arranged at optionalpositions within a selected one of the unit cell groups, respectively,in such a fashion that they separate each of the bit lines into twoportions, the separated bit line portions being connected by aninterconnection line.
 16. The ferroelectric random access memoryaccording to claim 15, wherein respective plate electrodes of the unitcells are connected to plate electrode lines spaced from one another ina row direction in such a fashion that one of unit cell groups eachconsisting of N unit cells is connected to an associated one of theplate electrode lines.
 17. The ferroelectric random access memoryaccording to claim 15, wherein respective plate electrodes of the unitcells are connected in common by a plate electrode line.
 18. Theferroelectric random access memory according to claim 15, whereinrespective plate electrodes of the dummy cells are connected to theground.
 19. The ferroelectric random access memory according to claim15, wherein a predetermined voltage is applied to respective plateelectrodes of the dummy cells.
 20. The ferroelectric random accessmemory according to claim 15, wherein respective plate electrodes of theunit cells are connected in common by a plate electrode line, to which apredetermined voltage is applied, and respective plate electrodes of thedummy cells are connected to the ground.
 21. The ferroelectric randomaccess memory according to claim 15, wherein two unit cells are arrangedin pair on each of the bit lines in such a fashion that they areconnected together in series, and the unit cell pairs are arranged in analternating fashion between neighboring ones of the bit lines.
 22. Theferroelectric random access memory according to claim 15, wherein thedummy cells are connected in common to a single dummy word line.
 23. Theferroelectric random access memory according to claim 15, whereinrespective capacitors of the unit cells are made of a ferroelectricfilm, and respective capacitors of the dummy cells are made of adielectric film.
 24. The ferroelectric random access memory according toclaim 23, wherein the capacitor of each dummy cell is a gate capacitorusing a dielectric film as a gate insulating film thereof.
 25. Theferroelectric random access memory according to claim 15, wherein thefirst switching transistor group comprises: a first switching groupconsisting of a plurality of switching transistors respectively arrangedon those of the bit lines corresponding to one of two interlaced bitline groups each consisting of interlaced bit lines, each of theswitching transistors in the first switching group serving to switch aconnection of the dummy cell, arranged on an associated one of the bitlines in the one interlaced bit line group, to the associated bit line,the switching transistors in the first switching group being connectedin common to a first control line; and a second switching groupconsisting of a plurality of switching transistors respectively arrangedon those of the bit lines corresponding to the other one of theinterlaced bit line groups, each of the switching transistors in thesecond switching group serving to switch a connection of the dummy cell,arranged on an associated one of the bit lines in the other interlacedbit line group, to the associated bit line, the switching transistors inthe second switching group being connected in common to a second controlline.
 26. The ferroelectric random access memory according to claim 25,wherein when data is stored in an optional one of the unit cells, thefirst and second switching groups are controlled to be switched to OFFstates thereof in response to a switching control signal externallyapplied thereto, respectively.
 27. The ferroelectric random accessmemory according to claim 25, wherein when data is read out from anoptional one of the unit cells, the first and second switching groupsare controlled in such a fashion that one of the first and secondswitching groups is switched to an ON state thereof in response to aswitching control signal externally applied thereto whereas the otherone of the first and second switching groups is switched to an OFF statethereof in response to a switching control signal externally appliedthereto.
 28. A ferroelectric random access memory comprising a pluralityof bit lines extending in one direction, a plurality of word linesextending in another direction perpendicular to the one direction, and aplurality of unit cells arranged in an M×N array while being connectedto associated ones of the lines, each of the unit cells consisting ofone transistor and one capacitor, wherein the unit cells are groupedinto a plurality of unit cell groups, each of the unit cell groupsconsisting of a plurality of unit cells connected to associated ones ofthe bit lines, respectively, in such a fashion that they are arranged inan interlaced fashion in a row direction or in a column direction, thoseof the bit lines connected to each of the bit lines being connectedtogether in series; wherein the bit lines are grouped into bit linegroups each consisting of N bit lines; further comprising: a dummy cellgroup consisting of a plurality of dummy cells each connected to one ofbit lines included in an associated one of the bit line pairs at anoptional position on the bit line, each of the dummy cells consisting ofone transistor and one capacitor; a first switching transistor groupconsisting of a plurality of switching transistors each serving toswitch a connection among the unit cells on one bit line included in anassociated one of the bit line groups respectively corresponding to thedummy cells in response to a control signal externally applied thereto;a second switching transistor group consisting of a plurality ofswitching transistors each serving to switch a connection between thebit lines included in an associated one of the bit line groupsrespectively corresponding to the dummy cells in response to a controlsignal externally applied thereto; and a third switching transistorgroup consisting of a plurality of switching transistors each serving toerase data stored in an associated one of the dummy cells in response toa control signal externally applied thereto; wherein respectivecapacitors of the dummy cells are made of a dielectric film having nospontaneous polarization characteristic; whereby when data is read outfrom an optional one of the unit cells on a selected one of the bitlines, a predetermined voltage outputted from an inverted bit lineneighboring to the bit line group including the selected bit line isprovided as a reference voltage required for a comparison with a voltagecorresponding to the read-out data.
 29. The ferroelectric random accessmemory according to claim 28, wherein respective plate electrodes of theunit cells are connected to plate electrode lines spaced from oneanother in a row direction in such a fashion that one of unit cellgroups each consisting of N unit cells is connected to an associated oneof the plate electrode lines.
 30. The ferroelectric random access memoryaccording to claim 28, wherein respective plate electrodes of the unitcells are connected in common by a plate electrode line.
 31. Theferroelectric random access memory according to claim 28, whereinrespective plate electrodes of the dummy cells are connected to theground.
 32. The ferroelectric random access memory according to claim28, wherein a predetermined voltage is applied to respective plateelectrodes of the dummy cells.
 33. The ferroelectric random accessmemory according to claim 28, wherein when each of the bit line groupsconsists of four bit lines, a first one of the four bit lines beingconnected with an associated one of the dummy cells, the secondswitching transistor group comprises: first switching transistors eachserving to connect the first bit line of an associated one of the bitline groups with a second one of the bit lines included in theassociated bit line group between an associated dummy cell and the unitcells; second switching transistors each serving to connect the firstbit line of an associated one of the bit line groups with a third one ofthe bit lines included in the associated bit line group between anassociated dummy cell and the unit cells; and third switchingtransistors each serving to connect the first bit line of an associatedone of the bit line groups with a fourth one of the bit lines includedin the associated bit line group between an associated dummy cell andthe unit cells.
 34. The ferroelectric random access memory according toclaim 33, wherein when data is read out from an optional one of the unitcells on a selected one of the four bit lines, one of the first throughthird switching transistors are controlled to be switched to an ON statethereof whereas the remaining switching transistors are controlled to beswitched to OFF states thereof, respectively.
 35. A ferroelectric randomaccess memory comprising a plurality of bit lines extending in onedirection, a plurality of word lines extending in another directionperpendicular to the one direction, and a plurality of unit cellsarranged in an M×N array while being connected to associated ones of thelines, each of the unit cells consisting of one transistor and onecapacitor, wherein the unit cells are grouped into a plurality of unitcell groups, each of the unit cell groups consisting of a plurality ofunit cells connected to associated ones of the bit lines, respectively,in such a fashion that they are arranged in an interlaced fashion in arow direction or in a column direction, those of the bit lines connectedto each of the bit lines being connected together in series; furthercomprising: a dummy cell group divided into a first dummy cell groupconsisting of a plurality of dummy cells connected in common to a firstdummy word line, and a second dummy cell group consisting of a pluralityof dummy cells connected in common to a second dummy word line, each ofthe dummy cells consisting of one transistor and one capacitor; and aswitching transistor group consisting of a plurality of switchingtransistors each serving to erase data stored in an associated one ofthe dummy cells in response to a control signal externally appliedthereto; wherein respective capacitors of the dummy cells are made of adielectric film having no spontaneous polarization characteristic;whereby when data is read out from an optional one of the unit cells ona selected one of the bit lines, a predetermined voltage outputted fromthat of dummy cells connected to an inverted bit line neighboring to theselected bit line is provided as a reference voltage required for acomparison with a voltage corresponding to the read-out data.
 36. Theferroelectric random access memory according to claim 35, wherein thedummy cell groups and the switching transistor group are arranged atoptional positions within a selected one of the unit cell groups,respectively.
 37. The ferroelectric random access memory according toclaim 36, wherein respective plate electrodes of the unit cells areconnected to plate electrode lines spaced from one another in a rowdirection in such a fashion that one of unit cell groups each consistingof N unit cells is connected to an associated one of the plate electrodelines.
 38. The ferroelectric random access memory according to claim 36,wherein respective plate electrodes of the unit cells are connected incommon by a plate electrode line.
 39. The ferroelectric random accessmemory according to claim 36, wherein respective plate electrodes of thedummy cells are connected to the ground.
 40. The ferroelectric randomaccess memory according to claim 36, wherein a predetermined voltage isapplied to respective plate electrodes of the dummy cells.
 41. Theferroelectric random access memory according to claim 36, wherein twounit cells are arranged in pair on each of the bit lines in such afashion that they are connected together in series, and the unit cellpairs are arranged in an alternating fashion between neighboring ones ofthe bit lines.
 42. The ferroelectric random access memory according toclaim 36, wherein respective capacitors of the unit cells are made of aferroelectric film, and respective capacitors of the dummy cells aremade of a dielectric film.
 43. The ferroelectric random access memoryaccording to claim 42, wherein the capacitor of each dummy cell is agate capacitor using a dielectric film as a gate insulating filmthereof.
 44. The ferroelectric random access memory according to claim36, wherein when data is stored in an optional one of the unit cells,one of the first and second switching groups is controlled to beswitched to an OFF state thereof in response to a switching controlsignal externally applied thereto, respectively, and the other switchinggroup is controlled to be switched to an ON state thereof in response toa switching control signal externally applied thereto.
 45. Aferroelectric random access memory comprising a plurality of bit linesextending in one direction, a plurality of word lines extending inanother direction perpendicular to the one direction, and a plurality ofunit cells arranged in an M×N array while being connected to associatedones of the lines, each of the unit cells consisting of one transistorand one capacitor, wherein the unit cells are grouped into a pluralityof unit cell groups, each of the unit cell groups consisting of aplurality of unit cells connected to associated ones of the bit lineswhile being connected to a plurality of word lines, respectively, insuch a fashion that they are arranged in an aligned fashion in a columndirection, those of the bit lines connected to each of the bit linesbeing connected together in series; further comprising: a dummy cellconnected to a dummy bit line and adapted to provide, to a selected oneof the bit lines, a reference voltage required for a data determinationwhen data is read out, the dummy cell consisting of one transistor andone capacitor; and a switching transistor serving to erase data storedin the dummy cell in response to a control signal externally appliedthereto; wherein the capacitor of the dummy cell is made of a dielectricfilm having no spontaneous polarization characteristic; whereby whendata is read out from an optional one of the unit cells on a selectedone of the bit lines, a predetermined voltage outputted from the dummycell connected to the dummy bit line is provided as a reference voltagerequired for a comparison with a voltage corresponding to the read-outdata.
 46. The ferroelectric random access memory according to claim 45,wherein respective plate electrodes of the unit cells are connected toplate electrode lines spaced from one another in a row direction in sucha fashion that one of unit cell groups each consisting of N unit cellsis connected to an associated one of the plate electrode lines.
 47. Theferroelectric random access memory according to claim 45, whereinrespective plate electrodes of the unit cells are connected in common bya plate electrode line.
 48. The ferroelectric random access memoryaccording to claim 45, wherein respective plate electrodes of the dummycells are connected to the ground.
 49. The ferroelectric random accessmemory according to claim 45, wherein a predetermined voltage is appliedto a plate electrode of the dummy cell.
 50. The ferroelectric randomaccess memory according to claim 45, wherein respective capacitors ofthe unit cells are made of a ferroelectric film, and the capacitor ofthe dummy cell is made of a dielectric film.
 51. The ferroelectricrandom access memory according to claim 45, wherein the capacitor of thedummy cell is a gate capacitor using a dielectric film as a gateinsulating film thereof.